The present invention relates to integrated circuit (IC) dies, and more particularly to designing an IC die having multiple rows of bond pads around its periphery, thereby enabling the die to be cut or scribed from the silicon wafer on which it is formed in multiple sizes.
In the last few decades, the electronics industry has literally transformed the world. Electronic products are used by, or affect the daily lives of, a large segment of the world's population. For example, telephones, television, radios, Personal Computers (PCs), laptop PCs, palmtop PCs, PCs with built-in portable phones, cellular phones, wireless phones, pagers, modems, and video camcorders, are just a few of the electronic products that have been developed in recent years and which have been made smaller and more compact, while providing more and/or enhanced functions than ever before. The integrated circuit (IC) die or IC chip, and the more efficient packaging of the IC die, have played a key role in the success of these products.
All of the devices listed above use many different size integrated circuit (IC) packages. The size of the IC die is determined in large part by the type of IC package in which the IC die is to be used. In most cases, the smallest IC die size is designed to reduce the cost of fabrication of the device.
There are four distinct stages in the manufacture of an IC die. The first stage is the material preparation. In this stage, the raw materials are mined and purified to meet semiconductor standards. The second stage consists of forming the material into wafers. The diameters of the wafers can vary between 1 and 12 inches. In the third stage, wafer fabrication, the IC dies are formed in and on the wafer. Up to several thousand identical devices can be formed on a single wafer, but typically 200 to 300 are more common. The area on the wafer occupied by the discrete device is called an IC die. Once the IC die has been formed on the silicon wafer, the wafer is cut or scribed to form the individual IC dies. In stage four, the IC die is housed or mounted within an individual protective package. Frequently, the IC die may be mounted with other components in a hybrid or multichip modules. Alternately, the IC die may be connected directly into a printed circuit board or other substrate to be used in an electronic device.
FIG. 1 shows a portion of a plan view of a wafer 100 having multiple IC dies formed thereon that is an example of the prior art structure of a typical IC die design. Typically, many IC dies 110 are formed on the wafer 100 using conventional technology. The IC electronic components (e.g., transistors and connector traces) are concentrated in the center of the IC die 110 and bond pads 120 are located on the periphery of the IC die 110 for connection to an IC package. There may be hundreds of IC dies 110 formed on a single wafer 100. The individual IC dies 110 are separated from each other on the wafer 100 by an area called a scribe street 130 or avenue. On either side of the scribe street 130 are scribe lines 140, also called saw lines. These scribe lines 140 also define the periphery of the individual IC die 110 once it is cut from the wafer 100. In current practice, the scribe street 130 is blank. This traditional design results in an IC die 110 of a particular size, determined by the design of the IC package and the fabrication technology.
Sometimes the need arises to alter the IC die size. For example, the electronic device with which the IC package is to be used may need to alter its performance parameters necessitating a change in the size of the die. In some cases, the IC die size is determined by the number of bond pads needed to connect to the IC package and the required spacing of the bond pads. In all cases, once the IC die size has been determined in the design stage, further changes in the IC die size result in a costly redesign process, effectively starting a new design process from the beginning. As a result, once the IC die is designed, changes cannot be made without re-designing and re-tooling. The IC die designer can use existing IC die sizes, but since the IC package size is set, the IC die may not be optimum. A fixed IC package size does not allow the IC die designer to evaluate the different options for optimized performance or cost savings without going to multiple designs and long fabrication cycle times.
Each IC device manufacturer typically has a preferred IC die design. In current practice, the IC package is optimized for a particular IC die, with the appropriate connection for the best performance of the device. The package is usually designed, tooled and manufactured before the IC die can be packaged.
In cases where an IC die is to be packaged in several different sized IC packages, the IC die has to be sized to fit all of the different options, which may increase the cost of the IC die and make the IC die incompatible with other IC packages. Also, when advances in the IC package technology result in a potential smaller-sized IC die, either the IC package or the IC die has to be redesigned or retooled in order to use the smaller IC die.
An assembly manufacturer may service different customers with different IC die sizes. However, this currently requires that the manufacturer design and stock several different IC packages for each of the different IC dies for their customers. Such multiple die/package stocking can be expensive.
In view of the above, it is evident that what is needed is an IC die design and wafer fabrication method that allows flexibility for different sized IC dies to be manufactured from the same wafer, allowing for multiple-sized IC dies to be used that are adaptable to different IC packages, thereby reducing the fabrication cycle time for new designs and making the design and implementation of different IC packages more cost effective.